Hardware Systems - Chip Design, AI/ML, ASICs, FPGAs
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"after 11 technical interviews"
"your work has been accepted into our codebase"
interviews are getting out of hand
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the worst part about being self-made is having to learn tennis at 30 instead of 8
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I was confused when the new intern said my name 10 times in the span of a 2 minute conversation,
then I saw this on his desk:
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as an electrical engineer, i decided to try the software thing
but guys
where are the integrals?
is it this "int" thing?
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Top Gun was 80s propaganda to make young men aspire to become naval aviators but just end up working shitty jobs in the navy.
It worked.
Iron Man was 2000s propaganda to make young men aspire to become "genius, playboy, philanthropist," engineers but just end up working shitty javascript jobs.
It also worked.
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the problem with going to court is that you might put a perfectly good startup out of business 🥀
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a big green company that makes GPUs
has its own internal branch of VSCode
for chip design
do with that what you will
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is it normal that our cracked gen-z intern whispers
“weapons free”
every single time he opens Vim?
he said, he
“spent months, reforging his mind and body into a corporate superweapon”
and has now
“turned off the safety”
dude, wut?
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Computer architecture is 50% memory and 50% compute.
If you want to be a hardware engineer or a better software engineer read this
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they just sent me a follow up question, after this, about the code i wrote and how to fix something.
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cracked gen-z intern today said he
"disabled his internal monologue"
because
"thoughts are latency"
this is getting out of hand
is it normal that our cracked gen-z intern whispers
“weapons free”
every single time he opens Vim?
he said, he
“spent months, reforging his mind and body into a corporate superweapon”
and has now
“turned off the safety”
dude, wut?
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with only a software background you basically need to start over.
1. Digital electronics
- you need to understand what a flop is
- boolean logic and k-maps
- metastability
- memory
- finite state machines
- timing diagrams (setup/hold, propagation delay)
- synchronous vs asynchronous design
- combinational vs sequential logic
- clock domains and clock domain crossing
Resources:
- "Digital Design and Computer Architecture" by Harris & Harris
- nandland basics
2. Verilog / Hardware Description Languages
- modules, ports, signals
- continuous assignment vs procedural assignment
- blocking vs non-blocking assignment
- sensitivity lists
- RTL coding discipline (synthesizable subset)
- testbenches and simulation
- structural vs behavioral descriptions
Resources:
- "FPGA Prototyping by Verilog Examples" by Pong Chu
- nandland Verilog tutorials
- HDLBits (online practice problems)
3. Computer architecture
- datapaths and control paths
- registers, ALUs, multiplexers
- pipelines and hazards
- microcoded vs hardwired control
- instruction sets and decoding
- caches and memory hierarchies
- buses and interconnects
Resources:
- "Computer Organization and Design" by Patterson & Hennessy
- "Computer Architecture: A Quantitative Approach" by Hennessy & Patterson
4. FPGA architecture
- LUTs, flip-flops, carry chains
- block RAM and distributed RAM
- DSP slices and multipliers
- clocking resources (MMCMs, PLLs)
- IO blocks and SERDES
- resource utilization and constraints
Resources:
- Vendor user guides (Xilinx)
- nandland FPGA
- FPGA4Fun tutorials
5. Toolchain & workflow
- synthesis -> place & route -> bitstream
- constraint files (timing, pin mapping, clock definitions)
- timing closure and static timing analysis
- simulation before synthesis
- debugging with waveform viewers and ILAs
6. System design
- finite state machine design methodology
- streaming vs memory-mapped architectures
- interfacing with peripherals (UART, SPI, I2C, Ethernet)
- DMA and buffering
- soft CPUs (MicroBlaze, Nios II, RISC-V)
- system buses (AXI, AHB, Wishbone)
Resources:
- Xilinx AXI IP examples in Vivado
7. Hardware/software co-design
- partitioning work between FPGA logic and embedded CPU
- hardware accelerators for software bottlenecks
- co-simulation and HW/SW debug
- real-time constraints
Resources:
- Zynq SoC tutorials (Xilinx)
- “Designing Embedded Systems with FPGA” by Peter Athanas et al.
8. Mindset shift
- hardware is parallel, not sequential
- time is in cycles
- resources are physical
what’s the fastest way i can teach an intern with only DS&A knowledge everything about FPGAs and computer architecture? resources? hands on projects?
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we don't hire SWEs
we only hire 10x electrical engineers
and put the bad ones on the software team
to do the easy work
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openai is building its own chips and youre still trying to learn CUDA
pick up an fpga and learn
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someone said i should send them a handwritten thank you letter in case they change their mind
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Embedded interview question
Topic: power
You have a 3.3 V input rail but your system operates at 1.2 V.
What can you do?
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Jane Street's money printer FPGAs, optimized for high frequency trading,
run at <600MHz,
while your intel CPU from 20 years ago ran at some GHz.
Speed and being low latency are not only about clock speed.
This is the insane perception of quantum bulls—next NVIDIA. No, look at clock speed of NVDA or INTC and compare to gate speed of quantum.
GHz
Vs.
MHz, KHz or just Hz 😂
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you could literally be making $700k out
of college in FPGA design
but you thought a 70k javascript job in SF had better prospects
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College students: I can't choose between CS and EE
meanwhile the decision they're actually making:
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Drop out of CS for EE right now
there are infinite flavors of EEs after university
there are only three flavors of SWEs:
- react todo list app devs (frontend)
- crud api devs (backend)
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Google open sourcing an energy-efficient AI accelerator (NPU) was not on my bingo card
Bonus points: It has a 32-bit RISC-V ISA
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why would he lie
60k is a lot
it's a bit less than @laserboat999's PC
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SoC vs SiP for the interested:
SoC (System on Chip):
- A single die that integrates multiple system functions (CPU, GPU, memory, I/O...) onto one piece of silicon
SiP (System in Package):
- Multiple dies (even from different wafers/ node types) integrated into one package
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During interviews I have candidates increase their microphone sensitivity.
I tell them it's for cheating reasons but it's really so I can listen for a smoke detector beep
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During an interview, if you say "NDA" when discussing an internship you did
the wifi on my laptop will magically turn off and the call will drop
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my favorite part about high frequency trading
is that your intel CPU from 10 years ago runs at a higher frequency than the FPGA making billions
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> be me
> working late, friday night in the office
> i love being a startup founder in SF
> investors are happy
> wife is on a date with her boyfriend
> wife is happy
> life is great
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Embedded interview question
Topic: clocks and protocols
difficulty: easy-medium
A UART needs to run at 115200 baud with a 16 MHz clock and 16x oversampling.
Since 16 MHz / (16 * 115200) = ~8.68, you can’t get an exact divider.
What do you do?
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cracked intern hasn't gone home this week
dude is making $10k/week and sleeps on a yoga mat on the office floor
asked him how he likes the office showers
and he replied, "what showers?"
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Moores law enabled better and smaller chips
which enabled software to be less optimized than ever and for games to be 150GB
Hardware got better
Software got sloppier
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The highest alpha thing you can do as an EE grad wanting to do FPGA/ASIC design is
learn about CDC
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Don't learn VHDL.
If you were taught VHDL at university instead of Verilog, please comment the university name so everyone knows to not send their kids there.
name and shame.
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EE basics: Clock oscillators
A crystal osc relies on a quartz crystal reference combined with an oscillator circuit
A MEMS osc uses a silicon resonator as its frequency source and a PLL to correct it for manufacturing and temperature variations
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what do you mean i just bought a $3k macbook and it can't run any industry-grade ASIC/FPGA tools?
> Cadence?
nope
> Synopsis?
nope
> Vivado?
DONT EVENT THINK ABOUT IT
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this was the stupidest thing i ever learned as an EE
have not used it once and don't know anyone that does
just use your intuition for analog circuits
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There is no way on earth that TSMC has the design knowledge to create any advanced chip.
They do manufacturing of a specific text format (GDSII).
They have no knowledge of the levels of abstraction that get compressed into a description of how the transistors should sit.
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Electrical engineering 7th round interview question:
design a single layer pcb with an ESP32 for detecting radiation (make no mistakes).
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woke up to this
from the intern
"clanker birthgiver"
we have a meeting with HR on monday
is it normal that our cracked gen-z intern whispers
“weapons free”
every single time he opens Vim?
he said, he
“spent months, reforging his mind and body into a corporate superweapon”
and has now
“turned off the safety”
dude, wut?
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i actually thought ppl would find this funny
but i forgot that half the ppl here are either VCs or have VC funding lol
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